Have any questions?

Whatsapp Skype Email

Hisilicon 8K AI Camera Solution

Hi3559/Hi3559A Hisilicon 8K AI SoC SDK Free Download

Hisilicon Hi3559/Hi3559A camera SoC is a high-end processor supporting 8K UHD resolution and xNNIE neural networking capability. The new SoC support max 36 megapixel up to 8 sensor inputs, can be used for panoramic security camera, it supports H.265/HEVC video compression technology, built-in powerful dual-core Mali G71 GPU. It’s the first choice for AI powered security cameras. 

Download Hi3559A SDK (Software Development Kit) for Free

{josociallocker}https://pan.baidu.com/s/1eSrklf8   password: wpgw{/josociallocker}

Hi3559A key Specification

Processor Core
Dual-core ARM Cortex A73@1.8 GHz, 32 KB I cache, 64
KB D cache or 512 KB L2 cache
Dual-core ARM Cortex A53@1.2 GHz, 32 KB I cache, 32
KB D cache or 256 KB L2 cache
Single-core ARM Cortex A53@1 GHz, 32 KB I cache, 32
KB D cache or 128 KB L2 cache
Neon acceleration and integrated FPU
Dual-core ARM Mali G71@900 MHz, 256 KB cache
OpenCL 1.1/1.2/2.0
OpenGL ES 3.0/3.1/3.2
Sensor Hub
Integrated ARM Cortex M7@192 MHz
Integrated PMC, which supports only external reset
Internal POR
General peripheral IPs (UART, SPI, I2
and LSADC)
2-channel LSADC, seven UART interfaces, and eight
PWM interfaces
Video Encoding
H.264 BP/MP/HP
H.265 Main Profile/Main 10 Profile
I/P/B frame supported in H.264/H.265 encoding mode
MJPEG/JPEG Baseline encoding
A maximum of 8192 x 8640 resolution for H.264
A maximum of 16384 x 8640 resolution for H.265
Real-time multi-stream H.264/H.265 encoding capability:
− 7680 x 4320@30 fps+1080p@30 fps+7680 x 4320@2
fps snapshot
Maximum JPEG snapshot performance of 7680 x
4320@15 fps
CBR, VBR, AVBR, FIXQP, and QPMAP bit rate control
Maximum 200 Mbit/s output bit rate
Encoding of eight ROIs
Video Decoding
H.264 BP/MP/HP
H.265 Main Profile/Main 10 Profile
JPEG/MJPEG decoding
Maximum video decoding performance of H.264/H.265
7680 x 4320@30 fps or H.264/H.265 3840 x 2160@120fps
Maximum 7680 x 4320@15 fps JPEG decoding
Intelligent Video Processing
Visual computing processing capability
Quad-core DSP@700 MHz, 32 KB I cache, 32 KB IRAM,
or 512 KB DRAM
Dual-core NNIE@840 MHz neural network acceleration engine
Internal dual-sensor depth detection unit
Video and Graphics Processing
Anti-flicker for output videos and graphics
1/15.5x to 16x video scaling
360° or 720° panoramic stitching of up to 6-channel videos
1/15.5x to 16x graphics scaling
OSD overlaying of eight regions before encoding
Video graphics overlaying of two layers (video layer and graphics layer)
2-channel independent ISP processing of video inputs
from multiple sensors in TDM mode
Adjustable 3A functions (AE, AWB, and AF)
FPN removal
Highlight suppression, backlight compensation, gamma
correction, and color enhancement
DPC, NR, and 6-DOF DIS
3DNR, image enhancement, and DCI
LDC and fisheye correction
Picture rotation by 90° or 270°
Picture mirror and flip
BT.2020 WCG
Sensor built-in WDR, 4F/3F/2F frame-based/line-based WDR and local tone mapping
ISP tuning tools for the PC
Audio Encoding and Decoding
Voice encoding/decoding complying with multiple
protocols by using software
G.711, G.726, AAC, and other audio encoding formats
Audio 3A functions (AEC, ANR, and ALC)
Security Engine
AES, DES, and 3DES encryption and decryption
algorithms implemented by using hardware
RSA1024/2048/3072/4096 signature verification
algorithm implemented by using hardware
HASH-SHA1/224/256/384/512 and
HMAC_SHA1/224/256/384/512 tamper proofing
algorithms implemented by using hardware
Integrated 32-kbit OTP storage space and hardware
random number generator
VI interfaces
− Eight sensor inputs
− Maximum 32-megapixel (7680 x 4320) or 36-
megapixel (6000 x 6000) resolution
− 8-/10-/12-/14-bit RGB Bayer DC timing VI, up to 150 MHz clock frequency
− BT.601, BT.656, and BT.1120 VI interfaces
− Maximum 16-lane MIPI/LVDS/sub-LVDS/HiSPi/SLVS-EC interface for the serial sensor inputs
− Maximum 8-channel video inputs for the serial sensor inputs, supporting various working modes such as
1x16-lane/2x8-lane/4x4-lane/2x4-lane+4x2- lane/8x2Lane
− Compatibility with the electrical specifications of parallel and differential interfaces of various sensors
− Programmable sensor clock output VO interfaces
− HDMI 2.0, supporting maximum 4K@60 fps output
− 6-/8-/16-/24-bit RGB digital LCD output, supporting maximum 1920 x 1080@60 fps output
− 4-lane MIPI DSI output, supporting maximum 2.5 Gbit/s per lane frequency

Hi3559A Introduction from Hisilicon

Hi3559A V100 is a professional 8K ultra-HD mobile camera SoC. It supports 8K30/4K120 digital video recording with broadcast-level picture quality. It also supports multiple sensor inputs as well as the H.265 encoding output or movie level raw data output. It integrates the high-performance ISP and employs the advanced low-power process and architecture design. Hi3559A V100 provides excellent image processing capability. Hi3559A V100 supports the industry-leading multichannel 4K sensor inputs, multi-channel ISP image processing, HDR10 technology standard, and multi-channel panoramic hardware splicing. When supporting 8K30/4K120 video recording, Hi3559A V100 provides the 6-DOF DIS hardware, which reduces its dependence on the mechanical head. Hi3559A V100 provides efficient and rich computing resources to assist customers in developing consumer applications and industry applications. Hi3559A V100 integrates the dual-core A73 processor and dual-core A53 processor as well as the big.LITTLE architecture and dual operating systems, achieving balance between the power consumption and startup time. Hi3559A V100 supports the product miniaturization design because it uses the advanced 12 nm low-power process and miniaturization package and supports DDR4/LPDDR4 SDRAMs. With the stable and easy-to-use mobile SDK design provided by HiSilicon, Hi3559A V100 can assist customers in rapid product mass production.

Get My Latest Posts

Subscribe to get the latest updates.

Your email address will never be shared with any 3rd parties.