Hisilicon Hi3519 4K SoC Datasheet

As the next-generation H.265 SoC designed for the 4K UHD IP security cameras and Sport DV cameras, the Hi3519A integrates a new-generation ISP and adopts the latest H.265 compressed video encoder, advanced low-power technology, and low-power design. This SoC is based on ARM® big.LITTLE™ architecture that combined with a powerful ARM Cortex-A17 1.2GHz core and a ARM Cortex-A7 800MHz core. The ARM big.LITTLE processing uses separate cores with different computing powers within the same CPU. The Cortex A17 core, or "big" core, handles intensive tasks like 4K UHD / 2K @30fps video encoding, and the A7 less powerful core executes less intensive tasks like intelligent video analysis.

The Hi3519A supports 90°or 270° rotation and lens distortion correction, which meets requirements in various surveillance applications. It also fully supports 3A algorithms, which allow customers to design different types of IP cameras including the IP AF zoom module. The Hi3519A integrates the POR, RTC, and audio CODEC and supports various sensor levels and clock outputs, which significantly reduces the EBOM costs for the Hi3516A HD IP camera.

Key Specification

Processor Core

• - A7@ 800MHz，32KB I-Cache，32KB D-Cache /128KB L2 cache  
• - A17@ 1.2GHz，32KB I-Cache，32KB D-Cache /256KB L2 cache
• - Neon acceleration, integrated FPU
• - ARM big.LITTLE architecture 

Video Encoding

• - H.264 BP/MP/HP H.265 Main Profile
• - H.265 Main Profile
• - H.264/H.265 I/P/
• - MJPEG/JPEG Baseline

Video Encoding Performance

• A maximum of 16-megapixel resolution for H.264/H.265 encoding.
• H.264/H.265 encoding of multiple streams：
• 4Kx2K@30fps+720P@30fps
• 16-Megapixel@2fps
• JPEG snapshot 8-megapixel @30fps
• Supporting CBR/VBR bitrate control mode，ranging: 16kbit/s～100Mbit/s
• Encoding frame rate ranging from 1/16～60fps
• Encoding of eight ROIs

Intelligent Video Analysis

• - Integrated IVE, supporting various intelligent analysis applications such as motion detection, boundary security and video diagnosis 
• - 3D denoising, image enhancement, and dynamic contrast enhancement
• - Anti-flicker for output videos and graphics,  1/15.99x to 16x video scaling
• - 1/2x to 2x graphics scaling
• - OSD overlay pre-processing for eight regions
• - Video graphics overlaying of two layers (video layer and graphics layer)

ISP

• - Adjustable 3A functions (AE, AWB, and AF)
• - Noise reduction in FPN mode
• - Highlight compensation, backlight compensation, gamma correction, and color enhancement
• - Defect pixel correction, denoising, and digital image stabilizer
• - Defog
• - Lens distortion correction
• - Picture rotation by 90° or 270°
• - Mirroring and flipping
• - Digital WDR, 4F/3F/2F - Frame base/Line base WDR,  Tone mapping
• - ISP tuning tools for the PC

Audio Encoding/Decoding

• - Voice encoding/decoding in compliance with multiple protocols by using software
• - G.711, ADPCM, and G.726 protocols
• - AEC, ANR, and ALC

Security Engine

• - Various encryption and decryption algorithms using hardware, such as AES, DES, and 3DES
• - RSA1024/2048/4096 Signature verification algorithm
• - Hardware Tamper-resistant HASH algorithm, support HASH SHA1 / 256, HMAC SHA1 / 256 Algorithm
• - Integrated 512Bit OTP storage space and hardware random number generator

Video Interfaces

- Input

• − 8-/10-/12-/14-bit RGB Bayer DC timing VI, a maximum of 150 MHz clock frequency
• − BT.601, BT.656 or BT.1120 VI interface
• − 12xLane MIPI/LVDS/Sub-LVDS/HiSPi
• − Compatible with mainstream HD CMOS sensors provided by SONY, ON Semiconductor, OmniVision, Panasonic 
• − Compatibility with the electrical specifications of parallel and differential interfaces of various sensors
• − Programmable sensor clock output

- Output

• − One PAL/NTSC output for automatic load detection
• − One BT.1120/BT.656 VO interface for connecting to an external HDMI or SDI, up to 1080p@60 fps output, support LCD output

Audio Interfaces

• - Integrated audio CODEC, supporting 16-bit audio inputs and outputs
• - I2S interface for connecting to an external audio CODEC
• - Stereo Mic differential input, reducing background noise

Peripheral Interfaces

• - POR
• - One integrated high-precision RTC
• - One quad-channel SAR ADC
• - Five UART interfaces
• - IR Interface, I2C Interfaces, SSP master interfaces, GPIO Interfaces
• - Eight PWM interfaces (four independent interfaces and four multiplexed with other pins)
• - Two SDIO 3.0/SDIO3.0 interfaces, supporting SDXC
• - One USB 3.0/2.0 host/device port
• - One PCIe2.0 master/slave mode
• - RGMII/RMII/MII in 100/1000 Mbit/s full-duplex or half-duplex mode, PHY clock output, and TSO network acceleration

External Memory Interfaces

- DDR3/3L SDRAM interface

•     − One 32-bit DDR4/3/3L interface with the maximum frequency of 800 MHz (1.6 Gbit/s)
•     − Maximum capacity of 1024MB for a 16-bit DDR
•     − Maximum capacity of 2048MB for two 16-bit DDRs

- SPI NOR flash interface

•     − 1-, 2-, or 4-wire mode
•     − Support 3Byte, 4Byte address mode
•     − Maximum capacity of 32 MB

- SPI NAND flash interface

    − Maximum capacity of 512MB

- eMMC5.0 interface

•     − maximum support 64GByte z NAND Flash interface
•     − 8bit data width
•     − SLC, MLC − 4, 8, 24, 40, 64bit ECC 
•     − 8GBabove devices

- Booting from the SPI NOR flash, SPI Nand Flash or NAND flash

- Booting from eMMC

SDK

• - Linux-3.4-based SDK
• - High-performance H.264/H.265 PC decoding library

Physical Specifications

- Power consumption

•     − 1.5W typical power consumption @4K*2K
•     − Multi-level power-saving mode

- Operating voltages

•     − 0.9V core voltage
•     − 3.3 V I/O voltage and 3.8 V margin voltage
•     − DDR4/3/3L SDRAM interface voltage 1.2/1.5/1.35 V

- Package

•     − RoHS，TFBGA
•     − Body size of 15 mm x 15 mm
•     − 0.65mm (0.03 in.) ball pitch

Hi3519 Datasheet Download: Hisilicon Hi3519 Datasheet Brief